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About the setting of PLL1

Question asked by dongdong dong on Jul 5, 2018
Latest reply on Jul 12, 2018 by dongdong dong

Hello,I have a new problem about the setting of PLL1,please see the pictures:

this is a setting I tried,but I am failed,in this setting,I set the " PLLDIG_PLL1FD[FDEN] = 0b " In the reference manual,the PLL1 VCO should be 48MHz * 20 = 960MHz

isn't it?

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