Facing an issue with SDMA of i.MX 6SoloX cortex M4

[manikandanps]

 Facing an issue with SDMA of i.MX 6SoloX cortex M4:

1] using memory to ECSPI and ECSPI to memory transaction.

2] When the dma channels were started for ECSPI's Tx and Rx, both MOSI and MISO shows correct data on the CRO.

3] However upon channel completed, the destination memory buffer is always 0x00/0xFF.

4] using OCRAM as data memory from  <0x00928000> for 256KB. (using L2 cache memory as OCRAM).

What could be the reason ?

[manikandanps]

hi igor,

i got this working by setting appropriate value in bit field <RX_THRESHOLD> in register DMA Control Register (ECSPIx_DMAREG).

Thanks,

Manikandan P S

[manikandanps]

hi igor,

May i know the significance of the the below register in ECSPI:

Message Data Register (ECSPIx_MSGDATA)

how is it different from RXdata/TXdata register ?

Thanks,

Manikandan P S

[igorpadykov]

Hi manikandan

one can check RDC memory region mappings for ocram, look at similar
example ecspi sdma in i.MX6UL FreeRTOS:
Board Support Packages (7)
SDK2.2_iMX6UL_WIN(REV SDK2.2)
i.MX 6UltraLite Applications Processor | Single Arm® Cortex®-A7 @ 696 MHz |NXP 

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------