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IMX6UL - iomuxc config of RMII clock

Question asked by ehwsma on Jul 4, 2018



I'm currently working on the IOMUXC config of the ethernet RMII peripheral of the IMX6UL.


Is there a reason why in the evk examples (and all the documentation I could found on the internet), the configuration of the ENET1_TX_CLK is always "0x4001b031" ? What does the "4" stand for ? From the reference manual, bits 31-17 are reserved and should be "0".


Thanks in advance.




        /* ETHERNET 1 */
        pinctrl_enet1: enet1grp {
            fsl,pins = <
                MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN    0x1b0b0
                MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER    0x1b0b0
                MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00    0x1b0b0
                MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01    0x1b0b0
                MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN    0x1b0b0
                MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00    0x1b0b0
                MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01    0x1b0b0
                MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1    0x4001b031