As in MPC5777C, there are 8 Bus master, which are given in below table, if i am not wrong:
(Original Table at 9-1 in ref. mannual)
1. Suppose Core0, is running and want to provide access permission :
Is to achieve the above point 1 we need to configure M1UM,M1SM,M1PE bits in MPU_RGD0_WORD2/MPU_RGDAACn?
2. If Core1 is running and i want to provide access permission :
Is to achieve the above point 2 we need to configure M3UM,M3SM,M3PE bits in MPU_RGD0_WORD2/MPU_RGDAACn?
and thus similar way for Bus master
4(eDMA_A), we need to configure bits M4RE,M4WE
5(eDMA_B), we need to configure bits M5RE,M5WE
6(CSE/SIPI) we need to configure bits M6RE,M6WE and
for 7(FEC) we need to configure bits M7RE,M7WE
Like Below, what i have try to figure out, please let me know, if i am TRUE-
Is above register should mapped according to Physical master port OR Logical master ID?
Please help me..