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imx8m USDHC and adma2

Question asked by Neil Shipp on Jul 3, 2018
Latest reply on Jul 10, 2018 by Neil Shipp

In the imx8m reference manual, the section for the USDHC controller is a direct copy and paste of the IMX7D documentation and only covers 32 bit mode addressing.  Does the imx8m USDHC controller support 96 bit length ADMA2 descriptors and 64 bit addressing?  If not, that means all SDHC ADMA transfers to and from memory above 0xFFFF FFFF will need to be double buffered.

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