I want to set the S32K144 onto the very low power mode (VLPS) and disable the adc clocks as well.
Hi,Please have a look at Table 27-9, RM rev.7You can disable both the Bus interface clock and the ADCLK in PCC module.
The bus interface clock is gated off by the transition to VLPS anyway.And also, the FIRC, SOSC and SPLL clock sources must be disabled before the MCU enters VLPS (Section 27.4.4).
Anyway, the ADC module is idle when a conversion has completed and another conversion has not been initiated. When idle, the module is in its lowest power state.If all triggers are disabled, the module stays idle (Section 42.5).
Can disabling the ADC modules by writing into ADCH register, be an option that can be considered in this case?
Thank you, Aditya
Retrieving data ...