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Bringup P2041 hardware issues:

Question asked by yan wang on Jul 3, 2018
Latest reply on Jul 17, 2018 by alexander.yakovlev

Bringup P2041 hardware issues:

 

I failed to bringup a bare board no RCW word with P2041 cpu.

Following the test case:

test case1:

Power up the P2041 board with rcw src setting with hardcode word( any tye), after dessert Poreset signal, the reset_req_b pin of P2041 was always high "1",but Hreset pin of P2041 was driven to "0" level.

test case2:

Power up the P2041 board with rcw src setting with nor flash 8 bit width, after dessert Poreset signal, the reset_req_b pin of P2041 was "0" level, but Hreset pin of P2041 was driven to "0" level. the LCLK0 pin output a 6.25MHz clock, CS0 of P2041 output four valid chipset signals, We tested on P2041rdb with same setting case, the CS0 of P2041 output eight valid chipset signals.

Power up the P2041 board with rcw src setting with nor flash 16 bit width, after dessert Poreset signal, the reset_req_b pin of P2041 was "0" level, but Hreset pin of P2041 was driven to "0" level. the LCLK0 pin output a 6.25MHz clock, CS0 of P2041 output two valid chipset signals, We tested on P2041rdb with same setting case, the CS0 of P2041 output four valid chipset signals.

Power up the P2041 board with rcw src setting with SDHC cardafter dessert Poreset signal, the reset_req_b pin of P2041 was "0" level, but Hreset pin of P2041 was driven to "0" level. the SDHC clk pin output a 50KHz clock, cmd of SDHC output  signals, 

 

 

We can't connect to P2041 customer board  with error message " can't stop the core of "under all these cases with codewarrior tap, 

 

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