AnsweredAssumed Answered

flexcan driver issue

Question asked by Mohammed Talha on Jul 2, 2018
Latest reply on Jul 2, 2018 by igorpadykov

I'm working with udoo quad (IMX6q). I've got the can bus up and running. However i have run into a similar issue referred to in this blog post

https://community.nxp.com/message/432806?q=flexcan%20bug%20atomic 

 

iMX6 FlexCAN generates 'BUG: scheduling while atomic' on every CAN send

 

 

[ 187.633144] BUG: scheduling while atomic: swapper/0/0/0x00000102
[ 254.513103] INFO: rcu_preempt detected stalls on CPUs/tasks: { 0} (detected by 1, t=2439 jiffies, g=4294967258, c=4294967257, q=2)
[ 254.524955] Task dump for CPU 0:
[ 254.528201] swapper/0 D 804e8630 0 0 0 0x00000002

 

i'm currently working with udooneo(imx6sx) and udooquad(imx6q). Applying the patch suggested in the post above  fixed the issue on imx6sx board. But on udooquad it has become intermittent. It happens sometimes on "ifconfig can0 up" or when the communication is started. Below is the patch i have applied to both imx6sx and imx6q. I'm using kernel 3.14.56-r0 (yocto poky distro). 

 

 

 

---
drivers/net/can/flexcan.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 8de484b..42c8e63 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -340,7 +340,7 @@ static int flexcan_chip_enable(struct flexcan_priv *priv)
flexcan_write(reg, &regs->mcr);

while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
- usleep_range(10, 20);
+ udelay(10);

if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
return -ETIMEDOUT;
@@ -359,7 +359,7 @@ static int flexcan_chip_disable(struct flexcan_priv *priv)
flexcan_write(reg, &regs->mcr);

while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
- usleep_range(10, 20);
+ udelay(10);

if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
return -ETIMEDOUT;
@@ -378,7 +378,7 @@ static int flexcan_chip_freeze(struct flexcan_priv *priv)
flexcan_write(reg, &regs->mcr);

while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
- usleep_range(100, 200);
+ udelay(100);

if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
return -ETIMEDOUT;
@@ -397,7 +397,7 @@ static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
flexcan_write(reg, &regs->mcr);

while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
- usleep_range(10, 20);
+ udelay(10);

if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
return -ETIMEDOUT;
@@ -412,7 +412,7 @@ static int flexcan_chip_softreset(struct flexcan_priv *priv)

flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
- usleep_range(10, 20);
+ udelay(10);

if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
return -ETIMEDOUT;
--
2.7.4

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