we are having problems interfacing a i.mx7 SOM module to a Xilinx Kintex 7 FPGA over PCIE.
we were successful in designing a test board using a Xilinx Spartan 6 FPGA.
2 boards have been designed. A test board and a new product design.
a adapter board has also been produced that allows both the test and new product boards to be connected to a PC running linux in lieu of the i.mx7
i.mx7 is running linux which we downloaded from the compulab support site (not yocto). We have tried both the image from the website and one we have built from source and both act the same.
a) i.mx7 processor sourced from Compulab and is combination of a Base Board with i.mx7 SOM Module installed.
b) PCIE done over mini-pcie connector located on base board..
c) FPGA Xilinx Spartan 6
d) imx7 WORKS OK (driver / app software all work ok) lspci shows correct data
e) PC WORKS OK (driver / app software all work ok) lspci shows correct data
f) Debug R0 current state is 11
New Product design
a) I.mx7 processor combination of a Compulab SOM Module installed into our new product design Base Board.
b) PCIE done over direct connections on the PCB
c) FPGA Xilinx Kintex 7
d) i.mx7 WONT LINK (PCIE Never links) lspci shows nothing as it never linked.
e) PC WORKS OK. (driver / app software all work ok) lspci shows correct data
f) Debug R0 current state is 2
We have been working the problem with Xilinx for some time now with little progress so far. We have just started working with a new person there and hope to move forward. However, I'm turning to the NXP community here to see if any of you can help.
I can provide lots of details as to what we have done (which will go on forever) but I'm not sure what would be most helpful.
1. The Xilinx LTSSM goes through many of the states. In state 4 where its looking for data back from the i.mx7 it fails. It then proceeds to retry but never succeeds and eventually the i.mx7 driver gives up and flags an error -110 (I believe this is ETIMEOUT).
2. We see traffic on both the TX and RX connections.between the 2 devices. It appears detect etc are all working normally and since the design links when running against many different PC's running linux we believe that electrically the design is sound.
3. I have monitored the 2 i.mx7 PCIE debug registers used by the driver and nothing obvious stood out. It may be that I need to look at capturing the registers more often or perhaps there is a better way to debug this issue.
Now the big questions.
1. Have any of you had similar issues?
2. Are there additional registers I can access in the i.mx7 PCIE phy that provide more detail about it's state. Things like has the i.mx7 recieved any data, I'm waiting for something from the EP etc).
3. Are there any detailed debug guides we can use to chase this down? We have found some info on the web but none of those suggestions resolved the issue.
Any help or suggestions would be greatly appreciated.
I'm attaching a file with content from the 2 debug registers. 1 from the working test board and one from the new design. Let me know what else might help and I will get you anything I can.
PS We have already scoured the forums and google. Found many things some of which helped with some initial design flaws in the new board design which helped us get to the point where it works with PC's and not with i.mx7.