We've got a project that involves reading up to 6 ADC values simultaneously with a speed of minimum 20KHz per channel. All data channels has to be synced with each other up to an accuracy of ~±100uS. The data-width required is 12-16bits. The 20KHz reading frequency should be quite stable, but a small jitter is acceptable.
With a fast calculation this would sum up to ~20000*6*16 = 1,92MBit/s or 240kByte/s.
As we are using the IMX6UL in another project (with one internal ADC-channel in use) I was wondering if anyone has done or been successfull in modifying the driver to suit this purpose?
We now read our one channel though Sysfs via file-read which is very slow, we can only get sample rates up to around 1KHz while already utilizing 25% of the processor time. Also the sample jitter simultaneously gets really big because of highly differing read-times.
Another approach I was thinking of is adding an external ADC through SPI, but it would be so much easier if directly using the already present internal ADC. Just as the calculation showed a raw data stream of ~240kB/s, I don't think that this would be impossible at all. The data-stream would go to a ring-buffer in RAM and HD-write (FLASH) is only enabled by user input.
Kind regards and all help appreciated,