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T1024 SGMII (SERDES) ISSUE

Question asked by Ram Krishnan on Jun 28, 2018
Latest reply on Jul 12, 2018 by Ram Krishnan

We have a board in which the T1024  SRDS_PRTCL_S1 rcw is set to 0x6B. We have three SGMII lanes. Two lanes (SD1_TX/RX2 and SD1_TX/RX3) are connected to a Marvel Quad Phy 88E1340S. The third (SD1_TX/RX1) is connected to a Marvel 98DX167. The SGMII lanes going to the 881E340S work fine. One test is to put that serdes lane in loopback i.e (FE0EA8FC, FE0EA8BC) and see if the traffic comes back. In the above two cases it does come back. But in the third case if I put the lane in loopback nothing comes back. The third address is FE0EA87C which if I put in loopback , no traffic seems to come back. I have checked the SERDES registers and they seem to all indicate correct configuration. The two serdes PLL's are in locked state. I can talk to the 98DX167 using the MDDIO lines and see that the link-status for the port connected to the SGMII Lane 3 shows down.

 

The two questions I have are.

1. If I put the serdes lane in loopback and the traffic does not come back would that indicate a problem in the T1024 configuration or does it depend on external factor.

2. What else would I need to look at to isolate this issue ?

 

I have also contacted Marvell to see if they any suggestions. 

 

Thank you and any help is appreciated.

Ram Krishnan

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