I'm chasing down what appears to be screwball interrupt responses. Section 188.8.131.52 of the K24 reference manual states the chip has 16 interrupt priority levels. The MQX PSP cortex.h header states "#define CORTEX_PRIOR_IMPL (3) " which is manipulated into a left-justified 3-bit mask as required for the NVIC.
- Does the chip have 8 or 16 levels?
- If 16, is the use of 8 by MQX intentional?