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Number of K24 interrupt priorities?

Question asked by FRED WEDEMEIER on Jun 25, 2018
Latest reply on Jun 26, 2018 by FRED WEDEMEIER

I'm chasing down what appears to be screwball interrupt responses. Section 3.2.2.1 of the K24 reference manual states the chip has 16 interrupt priority levels. The MQX PSP cortex.h header states  "#define CORTEX_PRIOR_IMPL  (3) " which is manipulated into a left-justified 3-bit mask as required for the NVIC.

- Does the chip have 8 or 16 levels?

- If 16, is the use of 8 by MQX intentional?

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