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Apparent conflict in DMA documentation K22P144M120SF5V2RM

Question asked by Keith Smith on Jun 25, 2018
Latest reply on Aug 16, 2018 by MICHAEL HUSLIG

In the document, K22P144M120SF5V2RM.pdf, Rev 5 2015, in section 21.3 Memory map is listed DMA MUX channel configuration registers this shows 0x4002_1000 to channel 3, 0x4002_1001 to channel 2, etc.


An example on page 422 shows the expected mapping of 0x4002_1000 to channel 0, 0x4002_1001 to channel 1, etc.


Example eDMA code shows 0x4002_1000 map to channel 0.


Which mapping is correct?