I refer to the IMX6ULLRM Rev.1 and IMX6ULLIEC Rev. 1.2.
Following registers have the POWERDOWN bit.
I refer to the following community.
It seems that the POWERDOWN bit controls the power to the PLL in low power mode.
On the other hand,
It is described at P30 Table 15 in IMX6ULLIEC as the follows.
SYSTEM IDLE : 528 PLL is active, other PLLs are power down
LOW POWER IDLE : All PLLs are power down
SUSPEND : All PLLs are power down
It seems that the POWERDOWN bit does not control the Power for PLL in Low Power mode.
What does the POWERDOWN bit control?
The CCM_ANALOG_PLL_*** registers have four kinds of similar registers.
What is the difference for these registers?
How should we treat these registers?