CCM_ANALOG_PLL_*** registers and POWERDOWN bit

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CCM_ANALOG_PLL_*** registers and POWERDOWN bit

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eishishibusawa
Contributor III

Dear Sir

 

I refer to the IMX6ULLRM Rev.1 and IMX6ULLIEC Rev. 1.2.

 

Following registers have the POWERDOWN bit.

CCM_ANALOG_PLL_ARM

CCM_ANALOG_PLL_SYS

CCM_ANALOG_PLL_AUDIO

CCM_ANALOG_PLL_VIDEO

CCM_ANALOG_PLL_ENET

 

I refer to the following community.

https://community.nxp.com/message/936213

It seems that the POWERDOWN bit controls the power to the PLL in low power mode.

 

On the other hand,

It is described at P30 Table 15 in IMX6ULLIEC as the follows.

 

SYSTEM IDLE : 528 PLL is active, other PLLs are power down

LOW POWER IDLE : All PLLs are power down

SUSPEND : All PLLs are power down

 

It seems that the POWERDOWN bit does not control the Power for PLL in Low Power mode.

 

Q1.

What does the POWERDOWN bit control?

 

 

The CCM_ANALOG_PLL_*** registers have four kinds of similar registers.

 

The CCM_ANALOG_PLL_***

The CCM_ANALOG_PLL_***_SET

The CCM_ANALOG_PLL_***_CLR

The CCM_ANALOG_PLL_***_TOG

 

Q2.

What is the difference for these registers?

How should we treat these registers?

 

Best Regards,

Eishi SHIBUSAWA

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igorpadykov
NXP Employee
NXP Employee

Hi Eishi

>Q1. What does the POWERDOWN bit control?

it powers down pll.

>Q2. What is the difference for these registers?

***_SET,***_CLR,***_TOG are bit oriented registers used for convenience of programming,

bit "1" in register position sets,clear or toggle sorresponding bit in CCM_ANALOG_PLL_*** register

Best regards
igor
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eishishibusawa
Contributor III

Dear igorpadykov

Thank you for your reply.

 

Excuse me, but please tell me the following again.

***

>Q1. What does the POWERDOWN bit control?

it powers down pll.

***

 

I refer to the IMX6ULLRM Rev.1.

The following is described at P714 18.7.1 Analog ARM PLL control Register.

CCM_ANALOG_PLL_ARM[POWERDOWN] = 1 (Reset Value)

 

Q1.

Which is the power to ARM PLL ON or OFF when CCM_ANALOG_PLL_ARM[POWERDOWN] is "1"?

(Is the power to ARM PLL on or off just after reset.)

 

Best Regards,

Eishi SHIBUSAWA

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igorpadykov
NXP Employee
NXP Employee

Hi Eishi

sorry I could not undestand your question.

What is it really about:

a) about power down

or

b) reset value

Best regards
igor

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eishishibusawa
Contributor III

Dear igorpadykov

Thank you for your support.

I am sorry that I could not explain the question contents well.

 

Q1.

Is the CCM_ANALOG_PLL_ARM [POWERDOWN] bit controlling power to the ARM PLL?

 

 

I refer to the IMX6ULLRM Rev. 1.

It seems that the CCM_ANALOG_PLL_ARM[POWERDOWN] is 1 just after POR.

 

Q2.

If the power to ARM PLL is OFF when the CCM_ANALOG_PLL_ARM[POWERDOWN] is 1, the ARM core cannot execute anything.

The power to ARM PLL is ON when the CCM_ANALOG_PLL_ARM[POWERDOWN] bit is 1.

The power to ARM PLL is OFF when the CCM_ANALOG_PLL_ARM[POWERDOWN] bit is 0.

Is my understanding correct?

 

Best Regards,

Eishi SHIBUSAWA

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igorpadykov
NXP Employee
NXP Employee

Hi Eishi

>Q1. Is the CCM_ANALOG_PLL_ARM [POWERDOWN] bit controlling power to the ARM PLL?

yes. CCM_ANALOG_PLL_ARM[POWERDOWN] is 1 after POR, and PLL is powered down.

Core receives clock using bypass from 24MHz (24MHz oscillator).

BYPASS=1 : Bypass the PLL.

After start-up ROM reconfigures CCM_ANALOG_PLL_ARM, as described in sect.8.4.3 Clocks at boot time

i.MX6ULL RM.

Best regards
igor

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