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Detection of VSYNC

Question asked by Eishi Shibusawa on Jun 20, 2018
Latest reply on Jul 4, 2018 by Joan Xie

Dear Sir

 

Customer is considering to develop the system using i.MX6DualLite.

Customer wants to generate the interrupt to CPU core with VSYNC.

I think that i.MX6DL has two camera I/F, Parallel interface and MIPI CSI-2.

 

1. Parallel interface

I think that it is able to connect the VSYNC signal with GPIO when it use the Parallel interface for the camera I/F.

Q1.

Is my understanding correct?

 

2. MIPI CSI-2

Q2.

How is it able to detect the VSYNC and notice it to the CPU core when it use the MIPI for camera I/F?

Is there any register to detect the VSYNC when it use the MIPI for the camera I/F?

 

Best Regards.

Eishi SHIBUSAWA

 

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