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i.MX6 PCIe RX FIFO Full?

Question asked by mas sohy on Jun 18, 2018
Latest reply on Jun 21, 2018 by mas sohy



I have a trouble at PCIe between i.MX6 and Altera FPGA.

There is used yocto Linux as OS. I allocated memory space by pci_alloc_consistent() on device driver, FPGA write data to physical address of its memory.

At first, it was well. But if I transferred continuously, then i.MX6 cannot receive soon, RX FIFO full signal from i.MX6 asserted after it. I watched this behavior by Altera Signal Tap.

I am confused because PCIe RX of i.MX6 become full in spite of transfer rate is bery slow (about 1MB/s).

I am thinking that because FPGA write to memory directly, software (include device driver, OS) didn't relate it.


  1. i) Please tell me this recognition is correct or not. If it is correct, then I will focus to fix FPGA.


  1. ii) How do you think why does RX FIFO become full?