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Is fADCK (ADC conversion clock frequency) referring to the ADC clock source before it is being divided down?  I'm assuming its after.  But if so, doesn't the "Typical conversion time" example in 23.5.4.6.2 not meet the minimum since 8 MHz/8 = 1 MHz?

Question asked by Aaron Dunkin on Jun 15, 2018
Latest reply on Jun 20, 2018 by Edgar Eduardo Lomeli Gonzalez

Document Number: KL17P64M48SF6RM

16 bit SE output mode

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