I haven't been able to use MCGFFCLK from the slow clock on these part, although it works from the divided FLL external clock.
Here I have IREFS set to '1' but there is no output on MCGFFCLK (that is, peripherals clocked from it don't count). The slow clock is available as shown by the physically measured 32.8kHz on the CLKOUT pin.
On a K64 I have 50Mhz external clock divided by 1024 at the non-selected input to the FLL and, as shown in the next diagram where I simply set IREFS back to '0'
the internal peripherals on MCGFFCLK are correctly clocked (and count) at 24.4kHz.
The design is different to other parts with the "Sync" block having three inputs, one from the FLL input, one from the external reference input divided by 2 and one from the bus clock (60Mhz in both cases).
Presumably the clock is not being gated out due to the clock valid bit not being set.
- why does the 48kHz external clock input work but the internal 32.8kHz not?
- what would cause the clock validity check to not allow it? (Adjusting the external reference clock divide didn't change anything)
- is there some trick needed that is not described in the manual?
- has the operation been verified?