Hi,
I would like to ask what are the correct addresses of the IPU block in i.MX6S/DL/Q SoCs.
There is a difference in what the TRM says - System memory map:
Start address | End address | Size | Description
02A0_0000 | 02DF_FFFF | 4 MB | IPU-2
0260_0000 | 029F_FFFF | 4 MB | IPU-1
and what addresses are used in device trees:
ipu1: ipu@02400000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ipu";
reg = <0x02400000 0x400000>;ipu2: ipu@02800000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ipu";
reg = <0x02800000 0x400000>;
All other addresses are correct. The ones from TRM match with those from device tree.
Is this a bug in the device trees? Or in the TRM? Or some maggic is happaning in background?
Thanks,
Michal
Solved! Go to Solution.
Hi Michal
device trees values are correct (also one can check mx6.h), seems this is misprint in Reference Manual.
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
Hi Michal
device trees values are correct (also one can check mx6.h), seems this is misprint in Reference Manual.
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
OK, thank you Igor.
It is weird that it was not caught earlier. I found the wrong values in all three datasheet revisions for both the Solo/DualLite and Quad SoC.
Thanks again,
Michal
I'm not an expert, but I quess 0x2600000 and 0x2A00000 are the correct addresses.