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S32K142 SPI Read Operation Failed

Question asked by Jing Yin Wong on Jun 13, 2018
Latest reply on Sep 10, 2018 by 中当 陈

Hi NXP Team,

 

I'm facing an issue related to SPI read operation on S32K142.

I tried to read the status register of a Winbond W25Q80DV serial flash memory. The datasheet mentions that I need to send an instruction of "0x05" in order to read the status register.

My SPI settings is as follows:

 

PCC->PCCn[PCC_LPSPI0_INDEX] = 0;
PCC->PCCn[PCC_LPSPI0_INDEX] = 0xC6000000;

LPSPI0->CR = 0x00000000;
LPSPI0->IER = 0x00000000;
LPSPI0->DER = 0x00000000;
LPSPI0->CFGR0 = 0x00000000;

LPSPI0->CFGR1 = 0x00000001;

LPSPI0->TCR   = 0xD0000008;

LPSPI0->CCR   = 0x04090808;

LPSPI0->FCR   = 0x00000003;

LPSPI0->CR    = 0x00000001;

 

PCC->PCCn[PCC_PORTB_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTB */
PORTB->PCR[0]|=PORT_PCR_MUX(3); /* Port B14: MUX = ALT3, LPSPI0_SCK */
PORTB->PCR[1]|=PORT_PCR_MUX(3); /* Port B15: MUX = ALT3, LPSPI0_SIN */
PORTB->PCR[2]|=PORT_PCR_MUX(3); /* Port B16: MUX = ALT3, LPSPI0_SOUT */
PORTB->PCR[3]|=PORT_PCR_MUX(3); /* Port B17: MUX = ALT3, LPSPI0_PCS0 */

 

while((LPSPI0->SR & LPSPI_SR_TDF_MASK)>>LPSPI_SR_TDF_SHIFT==0);
/* Wait for Tx FIFO available */
LPSPI0->TDR = 0x05; /* Transmit data */
LPSPI0->SR |= LPSPI_SR_TDF_MASK; /* Clear TDF flag */


while((LPSPI0->SR & LPSPI_SR_RDF_MASK)>>LPSPI_SR_RDF_SHIFT==0);
/* Wait at least one RxFIFO entry */
recieve= LPSPI0->RDR; /* Read received data */
LPSPI0->SR |= LPSPI_SR_RDF_MASK; /* Clear RDF flag */

 

I could not read the data (receive = 0).

CS0 went to a high state after 8 clock cycles (expecting CS0 to go to high state after 16 clock cycles).

 

 

Please advise on how to resolve the issue.

 

Thank you.

 

Best regards,

Jing Yin

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