QIZ 1 : FILTA : Digital filter sampling delay , what kind of unit for FILTA?
QIZ2 : how to set FILTA? I need a example of application.
Solved! Go to Solution.
Hi,
All three encoder inputs (PhA, PhB, and index) require digital filtering.
The number of sample clocks is user programmable from 1 to 4,294,967,295 (0xFFFF FFFF).
The QEI Digital filter on phase A input register [FILTA] bits using to set the filter delay for phA input signal.
From below picture, the digital filter clock source is system clock.
For example:
If customer set the [FILTA] bits value to 0x10000 with system clock 72MHz, the filter delay will be 910us.
If customer set the [FILTA] bits value to 0x10000 with system clock 12MHz, the filter delay will be 5.5ms.
If customer want to filter the input glitch (200ns width), customer can set the [FILTA] bits value to 0x10 with system clock 72MHz.
Wish it helps.
Have a great day,
Mike
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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Hi,
All three encoder inputs (PhA, PhB, and index) require digital filtering.
The number of sample clocks is user programmable from 1 to 4,294,967,295 (0xFFFF FFFF).
The QEI Digital filter on phase A input register [FILTA] bits using to set the filter delay for phA input signal.
From below picture, the digital filter clock source is system clock.
For example:
If customer set the [FILTA] bits value to 0x10000 with system clock 72MHz, the filter delay will be 910us.
If customer set the [FILTA] bits value to 0x10000 with system clock 12MHz, the filter delay will be 5.5ms.
If customer want to filter the input glitch (200ns width), customer can set the [FILTA] bits value to 0x10 with system clock 72MHz.
Wish it helps.
Have a great day,
Mike
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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