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i.MX RT1050 with external 16-bit SDRAM and 16-bit SRAM

Question asked by Heath Pritchett on Jun 11, 2018
Latest reply on Jun 14, 2018 by Heath Pritchett

I am trying to configure the RT1050 to use the SEMC to interface to external 16-bit SDRAM and 16-bit SRAM(for fpga communication). I can get them to work independently, but when I combine them I get hardfault_handler.I am confused on CS and CE pin mux, as it seems that which ever one is declared first, will work. I have tried initializing the SRAM CE with kSEMC_MUXCSX2 and address of 0x8800001c and address 0x98000018 but always ends with hardfault. Am I correct in thinking that these can be used at the same time? Thanks in advance!

 

Using the following:

-IAR

-SDK_2.3.0_EVK-MIMXRT1050

-SDRAM init attached

-SEMC config

   /* Configure SDRAM. */
   sdramconfig.csxPinMux = kSEMC_MUXCSX0; //CS0
   sdramconfig.address = 0x80000000;
   sdramconfig.memsize_kbytes = 32 * 1024;//32 * 1024; /* 32MB = 32*1024*1KBytes*/
   sdramconfig.portSize = kSEMC_PortSize16Bit;
   sdramconfig.burstLen = kSEMC_Sdram_BurstLen4;//kSEMC_Sdram_BurstLen8;
   sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit;
   sdramconfig.casLatency = kSEMC_LatencyTwo;
   sdramconfig.tPrecharge2Act_Ns = 21;//18; /* Trp 18ns */
   sdramconfig.tAct2ReadWrite_Ns = 21;//18; /* Trcd 18ns */
   sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */
   sdramconfig.tWriteRecovery_Ns = 14; /* 12ns */
   sdramconfig.tCkeOff_Ns = (1000000000 / clockFrq);
   sdramconfig.tAct2Prechage_Ns = 42; /* Tras 42ns */
   sdramconfig.tSelfRefRecovery_Ns = 67;
   sdramconfig.tRefresh2Refresh_Ns = 60;
   sdramconfig.tAct2Act_Ns = 60;
   sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);
   sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */
   sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;
   sdramconfig.refreshBurstLen = 1;
   return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);

   /* Configure ALTERA.*/
   altera_config.cePinMux = kSEMC_MUXCSX0;//CS2 PIN C7 SEMC_CSX0 added for altera
   altera_config.address = 0x8401001c;//added for altera
   altera_config.memsize_kbytes = 32 * 1024;//added for altera
   altera_config.portSize = kSEMC_PortSize16Bit;//added for altera
   altera_config.burstLen = kSEMC_Sdram_BurstLen2;//added for altera
   altera_config.addr27 = kSEMC_MORA27_NONE;//added for altera
   altera_config.tReLow_Ns = 18;//added for altera
   altera_config.readCycle = 10;//added for altera
   altera_config.addrMode = altera_config.addrMode | (0x03 << 8);//added for altera
   return SEMC_ConfigureSRAM(SEMC, &altera_config, clockFrq);//added for altera

 

-SDRAM initialization 

   void BOARD_SDRAM_Init()
   {
   // Config IOMUX for SDRAM
   writeRam(0x401F8014,0x00000000); // EMC_00
   writeRam(0x401F8018,0x00000000); // EMC_01
   writeRam(0x401F801C,0x00000000); // EMC_02
   writeRam(0x401F8020,0x00000000); // EMC_03
   writeRam(0x401F8024,0x00000000); // EMC_04
   writeRam(0x401F8028,0x00000000); // EMC_05
   writeRam(0x401F802C,0x00000000); // EMC_06
   writeRam(0x401F8030,0x00000000); // EMC_07
   writeRam(0x401F8034,0x00000000); // EMC_08
   writeRam(0x401F8038,0x00000000); // EMC_09
   writeRam(0x401F803C,0x00000000); // EMC_10
   writeRam(0x401F8040,0x00000000); // EMC_11
   writeRam(0x401F8044,0x00000000); // EMC_12
   writeRam(0x401F8048,0x00000000); // EMC_13
   writeRam(0x401F804C,0x00000000); // EMC_14
   writeRam(0x401F8050,0x00000000); // EMC_15
   writeRam(0x401F8054,0x00000000); // EMC_16
   writeRam(0x401F8058,0x00000000); // EMC_17
   writeRam(0x401F805C,0x00000000); // EMC_18
   writeRam(0x401F8060,0x00000000); // EMC_19
   writeRam(0x401F8064,0x00000000); // EMC_20
   writeRam(0x401F8068,0x00000000); // EMC_21
   writeRam(0x401F806C,0x00000000); // EMC_22
   writeRam(0x401F8070,0x00000000); // EMC_23
   writeRam(0x401F8074,0x00000000); // EMC_24
   writeRam(0x401F8078,0x00000000); // EMC_25
   writeRam(0x401F807C,0x00000000); // EMC_26
   writeRam(0x401F8080,0x00000000); // EMC_27
   writeRam(0x401F8084,0x00000000); // EMC_28
   writeRam(0x401F8088,0x00000000); // EMC_29
   writeRam(0x401F808C,0x00000000); // EMC_30
   writeRam(0x401F8090,0x00000000); // EMC_31   
   writeRam(0x401F8094,0x00000000); // EMC_32
   writeRam(0x401F8098,0x00000000); // EMC_33
   writeRam(0x401F809C,0x00000000); // EMC_34
   writeRam(0x401F80A0,0x00000000); // EMC_35
   writeRam(0x401F80A4,0x00000000); // EMC_36
   writeRam(0x401F80A8,0x00000000); // EMC_37
   writeRam(0x401F80AC,0x00000000); // EMC_38
   writeRam(0x401F80B0,0x00000010); // EMC_39, DQS PIN, enable SION
   writeRam(0x401F80B4,0x00000000); // EMC_40
   writeRam(0x401F80B8,0x00000000); // EMC_41   

   // PAD ctrl
   //   drive strength = 0x7 to increase drive strength
   // otherwise the data7 bit may fail.
   writeRam(0x401F8204,0x000110F9); // EMC_00
   writeRam(0x401F8208,0x000110F9); // EMC_01
   writeRam(0x401F820C,0x000110F9); // EMC_02
   writeRam(0x401F8210,0x000110F9); // EMC_03
   writeRam(0x401F8214,0x000110F9); // EMC_04
   writeRam(0x401F8218,0x000110F9); // EMC_05
   writeRam(0x401F821C,0x000110F9); // EMC_06
   writeRam(0x401F8220,0x000110F9); // EMC_07
   writeRam(0x401F8224,0x000110F9); // EMC_08
   writeRam(0x401F8228,0x000110F9); // EMC_09
   writeRam(0x401F822C,0x000110F9); // EMC_10
   writeRam(0x401F8230,0x000110F9); // EMC_11
   writeRam(0x401F8234,0x000110F9); // EMC_12
   writeRam(0x401F8238,0x000110F9); // EMC_13
   writeRam(0x401F823C,0x000110F9); // EMC_14
   writeRam(0x401F8240,0x000110F9); // EMC_15
   writeRam(0x401F8244,0x000110F9); // EMC_16
   writeRam(0x401F8248,0x000110F9); // EMC_17
   writeRam(0x401F824C,0x000110F9); // EMC_18
   writeRam(0x401F8250,0x000110F9); // EMC_19
   writeRam(0x401F8254,0x000110F9); // EMC_20
   writeRam(0x401F8258,0x000110F9); // EMC_21
   writeRam(0x401F825C,0x000110F9); // EMC_22
   writeRam(0x401F8260,0x000110F9); // EMC_23
   writeRam(0x401F8264,0x000110F9); // EMC_24
   writeRam(0x401F8268,0x000110F9); // EMC_25
   writeRam(0x401F826C,0x000110F9); // EMC_26
   writeRam(0x401F8270,0x000110F9); // EMC_27
   writeRam(0x401F8274,0x000110F9); // EMC_28
   writeRam(0x401F8278,0x000110F9); // EMC_29
   writeRam(0x401F827C,0x000110F9); // EMC_30
   writeRam(0x401F8280,0x000110F9); // EMC_31
   writeRam(0x401F8284,0x000110F9); // EMC_32
   writeRam(0x401F8288,0x000110F9); // EMC_33
   writeRam(0x401F828C,0x000110F9); // EMC_34
   writeRam(0x401F8290,0x000110F9); // EMC_35
   writeRam(0x401F8294,0x000110F9); // EMC_36
   writeRam(0x401F8298,0x000110F9); // EMC_37
   writeRam(0x401F829C,0x000110F9); // EMC_38
   writeRam(0x401F82A0,0x000110F9); // EMC_39
   writeRam(0x401F82A4,0x000110F9); // EMC_40
   writeRam(0x401F82A8,0x000110F9); // EMC_41

   //   Config SDR Controller Registers/
   writeRam(0x402F0000,0x10000004); // MCR
   writeRam(0x402F0008,0x00030524); // BMCR0
   writeRam(0x402F000C,0x06030524); // BMCR1
   writeRam(0x402F0010,0x80000017); //RLK1B); // BR0, 32MB
   writeRam(0x402F0014,0x8200001B); // BR1, 32MB
   writeRam(0x402F0018,0x8400001B); // BR2, 32MB
   writeRam(0x402F001C,0x8600001B); // BR3, 32MB
   writeRam(0x402F0020,0x90000021); // BR4,
   writeRam(0x402F0024,0xA0000019); // BR5,
   writeRam(0x402F0028,0xA8000017); // BR6,
   writeRam(0x402F002C,0xA900001B); // BR7,
   writeRam(0x402F0030,0x00000021); // BR8,
   writeRam(0x402F0004,0x000079A8); //IOCR,SEMC_CCSX0 as NOR CE, SEMC_CSX1 as PSRAM CE,    SEMC_CSX2 as NAND CE, SEMC_CSX3 as DBI CE.   

   //writeRam(0x402F0004,0x00000008); // IOCR, SEMC_CCSX0 as SDRAM_CS1
   writeRam(0x402F0040,0x00000F31); // SDRAMCR0
   writeRam(0x402F0044,0x00652922); // SDRAMCR1
   writeRam(0x402F0048,0x00010920); // SDRAMCR2
   writeRam(0x402F004C,0x50210A08); // SDRAMCR3

   writeRam(0x402F0080,0x00000021); // DBICR0
   writeRam(0x402F0084,0x00888888); // DBICR1
   writeRam(0x402F0094,0x00000002); // IPCR1
   writeRam(0x402F0098,0x00000000); // IPCR2

   writeRam(0x402F0090,0x80000000); // IPCR0
   writeRam(0x402F009C,0xA55A000F); // IPCMD, SD_CC_IPREA
   SDRAM_WaitIpCmdDone();
   writeRam(0x402F0090,0x80000000); // IPCR0
   writeRam(0x402F009C,0xA55A000C); // SD_CC_IAF
   SDRAM_WaitIpCmdDone();
   writeRam(0x402F0090,0x80000000); // IPCR0
   writeRam(0x402F009C,0xA55A000C); // SD_CC_IAF
   SDRAM_WaitIpCmdDone();
   writeRam(0x402F00A0,0x00000033); // IPTXDAT
   writeRam(0x402F0090,0x80000000); // IPCR0
   writeRam(0x402F009C,0xA55A000A); // SD_CC_IMS
   SDRAM_WaitIpCmdDone();
   writeRam(0x402F004C,0x50210A09 ); // enable sdram self refresh again after initialization done.   

   }

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