Nigel Spon

I'm looking at the MCF54450 for a design and wondering ab...

Discussion created by Nigel Spon on Nov 7, 2008
Latest reply on Nov 13, 2008 by Nigel Spon
I'm looking at the MCF54450 for a design and wondering about what the minimal DDR2 SDRAM layout looks like. I don't need more than 256Kbyte, but it looks as though using a single DDR2 SDRAM would actually give better performance and similar cost/complexity to a 32-bit wide SRAM on the FlexBus. The caveat here is that the SDRAM seems to require series and parallel termination along with a 0.9V regulator for the parallel terminators. This seems a lot for just one chip that will be right next to the CPU. I see that AN-3522 remarks that "in limited cases, parallel termination may not be needed". Thats nice to know, but a bit vague. So my question is:

Has anyone got an MCF5445x running with a single DDR2 SDRAM chip, and if so, what termination scheme did you use?

Thanks,
Nigel

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