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Bare metal ethernet implementation for the cortex M4

Question asked by Belic Stefan on Jun 10, 2018
Latest reply on Jun 11, 2018 by Belic Stefan

Hallo everyone, i am trying to implement a bare metal applikation for the cortex M4 that send ethernet frames at defined intervals. I have read the datasheet on how the ethernet registers are setup and the options it offers, but i was not able to understand how the data is actually moved to and from the ethernet FIFO. In the block diagram its shown that an uDMA is used, but no explanation on how to access it are given. It would be great if someone has more information, or even an simple answer on how to do it.

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