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DDR3 IMX6Q

Question asked by Matt Moranda on Jun 7, 2018
Latest reply on Jun 13, 2018 by Yuri Muhin

I've been simulating a Layout using the IMX6 and 4 DDR3
MT41K127M16 chips. The ADDRESS, COMMAND and CNTRL lines are routed using a Tree topology with two chips on the bottom of the board and two on top. Now I notice when I simulate this topology in Hyperlynx at 1.875 ns clock cycles inspecting clk and address signals , that the address is slower than the clk by about 100ps. To remedy this it is necessary to make the clk quite a bit longer than the clk well out of the range of 200 mils as suggested in the hardware development for imx6q manual. The clk needs to be about an 1 inch - 2 inches longer than the address signals to have the timing match or to have the address signal slightly ahead of the clk. If I use any other topology for routing suggested by Micron/ Jedec references this lag goes away. I know that with DDR3 the extra capacitance in the loading on the tree topology causes this delay problem, yet from other designs I have seen this routing can still be made to work. I have simulated another open source files that uses this same set up and the same delay is seen. Is this common and is there a way to handle it with write leveling or with programmed clk skew or something like this?  I attached an image of an eye diagram of the CLK vs the A10 address signal from the simulation I mentioned . I used a single end of the clk signal to align it with the same voltage reference as the A10 signal. The clk is orange in the simulation and A10 is light blue. Any suggestions or assistance anyone could offer me based on this would be appreciated.CLKvsADD

 

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