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LIN FSL_LIN_2.x_STACK_Package_4.5.9 : SCI Receive Data Register Full Interrupt set while transmitting

Question asked by Salman Shaikh on Jun 7, 2018
Latest reply on Jun 12, 2018 by Salman Shaikh



I am using LIN FSL_LIN_2.x_STACK_Package_4.5.9 package to implement a master LIN node. The communication is working fine but I am intrigued to know how is RDRF bit in SCISR1 set while transmitting data.