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i.MX RT 1052

Question asked by zhang yanming on Jun 7, 2018
Latest reply on Jun 14, 2018 by Yuri Muhin

Lately,I test the i.MX RT 1052 chip,using the cortex-M7 kernel,I put the code in the Out of chip memory ,Program variable in the DTCM,when i test,I enable I-cache and D-cache,the algorithm test time is 14S. when I enable I-cache and disable D-cache,the algorithm test time is 109S,The kernel access to DTCM is not affected by the D-cache,but the test result is non-conformity ,so i want to get the answer,please.thank you.

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