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on the fly chop mode of P2020 DDR controler

Question asked by yansong zhu on Jun 6, 2018
Latest reply on Jun 7, 2018 by yansong zhu

I will use DDR3 on the P2020 platform. But I have noticed that the DDR controler must be setted in 8-beat burst mode when using 32-bit bus mode and in 4-beat burst mode when using 64-bit bus mode with DDR_SDRAM_CFG[8_BE]. So, I have some question.

Q1: Is that because the cache lines on the e500 core are 32 bytes wide ? So the burst length multiplied bus wide must equals 32bytes ?

Q2: When I using 64-bit bus mode with DDR_SDRAM_CFG[8_BE] = 0 and DDR_SDRAM_CFG_2[OBC_CFG] = 1, does it mean that the DDR controler can access the DDR3 by using BL8 or BC4 ? If that is true, how to explain the Q1 ?

Q3: When I using 64-bit bus mode with DDR_SDRAM_CFG[8_BE] = 0 and DDR_SDRAM_CFG_2[OBC_CFG] = 0, does it mean that the DDR controler can access the DDR3 only by using BC4 ?

Q4: If the DDR3 only can be accessed by 4-beat burst length once on P2020 platform, does it mean that the performance of 64-bit bus mode is not much higher than the performance of 32-bit bus mode ?

Q5: When I use the ECC function in 32-bit bus mode, is the MDQ[32]~MDQ[39] used as the ECC[0]~ECC[7] ? 

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