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MPC5746R Clock Mode Switch causes reset

Question asked by Ron Lewis on Jun 6, 2018
Latest reply on Jun 27, 2018 by Peter Vlna

I am having an issue where a mode switch is causing the processor to reset.  The odd thing is that with the debugger attached and a breakpoint after the transition the processor does not reset.  See Code below, which was generated with the "MPC574xR_Clock_Calculator_Rev3"  excel doc.  I also don't find any relevant info in the exception registers?  Is there another place to look for clock configuration faults/errors?

 

//Enable XOSC, PLL0, PLL1, and enter RUN0 with PLL1_PHI as the system clock (200 MHz).
void Sysclk_Init(void)
{
         MC_CGM.AC3_SC.R = 0x01000000;  //Connect XOSC to the PLL0 input.
         MC_CGM.AC4_SC.R = 0x03000000;  //Connect PLL0_PHI1 to the PLL1 input.
     
        MC_ME.RUN_PC[0].B.DRUN = 1;     
        MC_ME.RUN_PC[0].B.RUN0 = 1;
       
        //Enable external oscilator
        MC_ME.DRUN_MC.B.XOSCON = 1;

        // Set PLL0 as system clock
        MC_ME.DRUN_MC.R = 0x00130071;
     
        PLLDIG.PLL0DV.R = 0x50022028;  //PREDIV = 2, MFD = 40, RFDPHI = 2, RFDPHI1 = 10
       
         //Mode transition to enter RUN0 mode:
         MC_ME.MCTL.R = 0x30005AF0;  //Enter RUN0 Mode & Key
         MC_ME.MCTL.R = 0x3000A50F;  //Enter RUN0 Mode & Inverted Key

        while(!MC_ME.GS.B.S_XOSC);              //ME_GS Wait for PLL stabilization.
        while(!MC_ME.GS.B.S_PLL0);              //ME_GS Wait for PLL stabilization.
         while(MC_ME.GS.B.S_MTRANS){};  //Wait for mode transition to complete
         while(MC_ME.GS.B.S_CURRENT_MODE != 3){};  //Verify RUN0 is the current mode
     
       
        //Set PLL0 to 400 MHz with 20 MHz XOSC reference.
         PLLDIG.PLL0DV.R = 0x50012028;  //PREDIV = 2, MFD = 40, RFDPHI = 1, RFDPHI1 = 10

        MC_ME.RUN_MC[0].R = 0x001300F4;
         //Set PLL1 to 200 MHz with 40 MHz PLL0_PHI1 input.
         PLLDIG.PLL1DV.R = 0x00020014;  //MFG = 20, RFDPHI = 2
         PLLDIG.PLL1FD.R = 0x00000000;  //Disable PLL1 fractional divider.
     
        //Mode transition to enter RUN0 mode:
         MC_ME.MCTL.R = 0x40005AF0;  //Enter RUN0 Mode & Key
         MC_ME.MCTL.R = 0x4000A50F;  //Enter RUN0 Mode & Inverted Key

        //Reset occurs after this line, but does not reset if debuggin and breakpoint on next line 
        while(!MC_ME.GS.B.S_XOSC);              //ME_GS Wait for PLL stabilization.
        while(!MC_ME.GS.B.S_PLL0);              //ME_GS Wait for PLL stabilization.
        while(!MC_ME.GS.B.S_PLL1);              //ME_GS Wait for PLL stabilization.
         while(MC_ME.GS.B.S_MTRANS){};  //Wait for mode transition to complete
         while(MC_ME.GS.B.S_CURRENT_MODE != 4){};  //Verify RUN0 is the current mode
       
        // Reset occurs before the call to InitPeriClkGen()
        InitPeriClkGen();
}
void InitPeriClkGen(void)
{
         //SYS_CLK is 200 MHz.
         MC_CGM.SC_DC[0].R = 0x80000000;  //CHKR_CLK, COMP_CLK, FXBAR_CLK, BD_CLK at system clock divided by 1 (200 MHz).
         MC_CGM.SC_DC[1].R = 0x80010000;  //SXBAR_CLK and LINCLK (synchronous) at system clock divided by 2 (100 MHz).
         MC_CGM.SC_DC[2].R = 0x80030000;  //PBRIDGE_x_CLK at system clock divided by 4 (50 MHz).
     
        MC_CGM.AC0_SC.R = 0x02000000;  //Select PLL0_PHI as source of Auxiliary Clock 0
         MC_CGM.AC0_DC0.R = 0x80040000;  //PER_CLK: Enabled at Auxiliary Clock 0 divided by 5 (80 MHz).
         MC_CGM.AC0_DC1.R = 0x80070000;  //SD_CLK: Enabled at Auxiliary Clock 0 divided by 8 (50 MHz).
         MC_CGM.AC0_DC2.R = 0x80040000;  //SAR_CLK: Enabled at Auxiliary Clock 0 divided by 5 (80 MHz).
         MC_CGM.AC0_DC3.R = 0x80040000;  //DSPI_CLK0: Enabled at Auxiliary Clock 0 divided by
         MC_CGM.AC0_DC4.R = 0x80040000;  //DSPI_CLK1 and LINCLK (asynchronous): Enabled at Auxiliary Clock 0 divided by 5 (80 MHz).
     
         MC_CGM.AC1_SC.R = 0x01000000;  //Select XOSC as source of Auxiliary Clock 1
         MC_CGM.AC1_DC0.R = 0x80000000;  //RF_REF: Enabled at Auxiliary Clock 1 divided by 1 (20 MHz).
     
         MC_CGM.AC2_SC.R = 0x02000000;  //Select PLL0_PHI as source of Auxiliary Clock 2
         MC_CGM.AC2_DC0.R = 0x80070000;  //SENT_CLK: Enabled at Auxiliary Clock 2 divided by 8 (50 MHz).
     
         //PLL0 and PLL1 are configured in SysClk_Init function.
     
         MC_CGM.AC5_SC.R = 0x02000000;  //Select PLL0_PHI as source of Auxiliary Clock 5
         MC_CGM.AC5_DC0.R = 0x80030000;  //eTPU_CLK: Enabled at Auxiliary Clock 5 divided by4 (100 MHz).
         MC_CGM.AC5_DC1.R = 0x80030000;  //eMIOS_CLK: Enabled at Auxiliary Clock 5 divided by 4 (100 MHz).
     
         MC_CGM.AC6_SC.R = 0x02000000;  //Select PLL0_PHI as source of Auxiliary Clock 6
         MC_CGM.AC6_DC0.R = 0x00130000;  //CLKOUT: Disabled.
     
         MC_CGM.AC8_SC.R = 0x01000000;  //Select XOSC as source of Auxiliary Clock 8
         MC_CGM.AC8_DC0.R = 0x80000000;  //CAN_CLK: Enabled at Auxiliary Clock 8 divided by 1 (20 MHz).
     
         MC_CGM.AC9_SC.R = 0x01000000;  //Select XOSCas source of Auxiliary Clock 9
         MC_CGM.AC9_DC0.R = 0x80000000;  //RTI_CLK: Enabled at Auxiliary Clock 9 divided by 1 (20 MHz).
     
         MC_CGM.AC10_SC.R = 0x00000000;  //Select IRCOSC as source of Auxiliary Clock 10
         MC_CGM.AC10_DC0.R = 0x000F0000;  //FEC clocks: Disabled.
        
}

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