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Issue about "RALAT" for LPDDR2 in IMX6Q

Question asked by shuai wang on Jun 6, 2018

In the IMX6Q reference manual, the MMDC chapter has a register "MMDCx_MDMISC", as the RALAR described" in lpddr2 mode 2 extra cycles will be added internally in order to compensate tDQSCK delay". If this field set 5, that means total 5+2 cycle will be added in lpddr2 device?