Issue about "RALAT" for LPDDR2 in IMX6Q

[shuaiwang]

In the IMX6Q reference manual, the MMDC chapter has a register "MMDCx_MDMISC", as the RALAR described" in lpddr2 mode 2 extra cycles will be added internally in order to compensate tDQSCK delay". If this field set 5, that means total 5+2 cycle will be added in lpddr2 device?

[gusarambula · Accepted solution]

Hello Shuai Wang,

Your assumption is correct, in the case of LPDDR2 mode two cycles would be added internally so if you select 5 in this field you would have 5+2 cycles added.

Regards,