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Device Tree Address Ranges for NOR, NAND & CPLD

Question asked by Embedded Engineer on Jun 6, 2018
Latest reply on Jun 12, 2018 by Embedded Engineer

I am trying to understand following part of device tree generated with T1042D4RDB kernel image:

localbus@ffe124000 {
        reg = <0xf 0xfe124000 0x0 0x2000>;
        ranges = <0x0 0x0 0xf 0xe8000000 0x8000000
                  0x2 0x0 0xf 0xff800000 0x10000
                  0x3 0x0 0xf 0xffdf0000 0x8000>;
        #address-cells = <0x2>;
        #size-cells = <0x1>;
        compatible = "fsl,ifc", "simple-bus";
        interrupts = <0x19 0x2 0x0 0x0>;

        nor@0,0 {
            #address-cells = <0x1>;
            #size-cells = <0x1>;
            compatible = "cfi-flash";
            reg = <0x0 0x0 0x8000000>;
            bank-width = <0x2>;
            device-width = <0x1>;

        nand@2,0 {
            #address-cells = <0x1>;
            #size-cells = <0x1>;
            compatible = "fsl,ifc-nand";
            reg = <0x2 0x0 0x10000>;

        cpld@3,0 {
            compatible = "fsl,t1040d4rdb-cpld", "fsl,deepsleep-cpld";
            reg = <0x3 0x0 0x300>;

Now I have following questions regarding above snippet:

1.  From the ranges property of localbus node, we can see that NOR, NAND and CPLD are mapped to parent's physical addresses 0xfe8000000, 0xfff800000 & 0xfffdf0000 respectively. Where do we get these parent's addresses from?


2.  Relating to first question, if I want to add 3 NOR flashes (replacing NAND and CPLD) on my custom board, what parent addresses will I use for them?


3.  NOR flash on RDB is 256MB and NAND flash is 1GB, then why the size in ranges property is 0x8000000 (128MB) for NOR and 0x10000 (64KB) for NAND flash?


4.  Ranges property of the localbus node shows that the NOR, NAND and CPLD are on chip selects 0, 2 and 3 respectively, but the schematic of RDB shows that the NOR, NAND and CPLD are connected to chip selects 0,1 & 2. Why is this discrepancy?


Can someone clarify my confusions over these queries?