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RESET pin

Question asked by Eishi Shibusawa on Jun 4, 2018
Latest reply on Jun 7, 2018 by richard_stulens

Dear Sir

 

I refer to the VYBRIDFSERIESEC Rev.9.

It is described as the follows at P69 NOTE.

"RESET pin has a external weak pull UP requirement if LPDDR2 memory is required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on."

 

Q1.

Which is the RESET pin either T4 (RESET / RESET OUT) or D6 (DDR_RESET)?

 

Best Regards,

Eishi SHIBUSAWA

 

Dear NXP member

 

How about this case?

Would you please reply.

 

Best Regards,

Eishi SHIBUSAWA

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