I refer to the VYBRIDFSERIESEC Rev.9.
It is described as the follows at P69 NOTE.
"RESET pin has a external weak pull UP requirement if LPDDR2 memory is required to support content retention in the device low power modes where core voltage is off but DRAM voltage is on."
Which is the RESET pin either T4 (RESET / RESET OUT) or D6 (DDR_RESET)?
Dear NXP member