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How can I keep DDR3 RAM content when performing warm reboot?

Question asked by Christian Aue on May 31, 2018
Latest reply on Jun 13, 2018 by Christian Aue

Hi everyone,


we're using an i.MX6Quad on a custom board with 2 GByte DDR3 RAM.
We would like to perform a watchdog WARM reset while keeping the data in the RAM valid.

In our scenario it would look like so:
1. watchdog warm reset triggered by kernel code
2. Bootrom
3. U-Boot SPL in SRAM -> should detect the warm reset cause and therefore not configure MMDC
4. U-Boot in DDR3
5. Kernel in DDR3


When connecting to the U-Boot preloader (SPL) via Lauterbach JTAG-Debugger, I can see that the MMDC has lost all of its settings like e.g. ammount of row and column bits, RAM timings etc.
Is this the expected behaviour when performing a warm reset?


My initial expectation was that the MMDC would keep all its RAM settings. I also would have guessed that the MMDC is indicating that it is in self refresh mode by asserting bit DVACK in register MAPSR.


I then checked the following settings:

SRC_SCR[warm_reset_enable] -> bit is programmed
SRC_SCR[warm_rst_bypass_count] -> Wait 16 XTALI but also changed it to 0x00 in order to make it wait indefinetly for the MMDC handshake
CCM_CCDR[17:16] -> handshake signals are NOT masked


What steps are necessary to get access to the DDR3 RAM again whithout changing its content?


best regards,