I have question about ENGcm11891 which is described in IMX25CE Rev. 7.1.
Does the timing of OE deassertion synchronize with the address switching ?
What I care about is that if / OE is deasserted at the timing of latching data, ROM can not output data,
so I think that it affects the data to be acquired, but when we confirmed by oscilloscope, address change timing It seems that / OE is deasserting.
At this timing, since it is different from the timing of latching data, we think that it can be designed so that there is no problem.
Does the CE deassert in synchronization with the change of the address signal at the completion of the burst access ?