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Shape of single ended DDR3 clock

Question asked by Torben Klein on May 29, 2018
Latest reply on May 30, 2018 by Torben Klein

Hi,

 

I have received the prototypes of a custom board I designed with an i.MX6ULL and DDR3L RAM. I use one 16-Bit RAM IC. I have finished calibrating the RAM and everything seems to run fine so far (tests in a climatic chamber are still to come). Now I measured the clock signal of the RAM to see if the termination is ok. In the picture I measured CLK_N to GND with an active probe. I am wondering why there is a change in the amplitude of the signal.

 

clk_n to GND

 

Everything seems to be within the allowed limits but I want to understand why the amplitude is changing like it is. Since this is the clock my understanding is that only the CPU is driving this signal, so I didn't expect to see something like this. In the design I use 100Ohm between the clk lines as termination. I do not use VTT termination. I measured this while running stress test tool v2.8.

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