U-BOOT hangs on LS1046 custom board

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U-BOOT hangs on LS1046 custom board

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gaborkocsis
Contributor III

Hi, Everybody

We have a custom board with LS1046. I have made my own U-Boot based on the original U-Boot shipped with LS1046ARDB.

It stucks after board initialization.

I've traced the program flow and found the followings:  
-  'board_init_f()' function run through correctly (The messages appear on a UART terminal). 
-  'board_init_r()' function couldn't get the control 
-   between these two functions there is a program relocation 
    (that    relocates the u-boot code to the DDR) 
    and 
    the c_runtime_setup routine  

The DDR configuration probably correct, a simple read-write test program doesn't show any error.  
Our custom board differs the from original LS1046ARDB at the DDR, we have 4 GB DDR SDRAM on our board.

What could the problem be?

Thanks in advance

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2 Replies

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yipingwang
NXP TechSupport
NXP TechSupport

Hello Gabor Kocsis,


You could refer to this documenthttps://community.nxp.com/docs/DOC-331981  to debug u-boot with CodeWarrior for ARMv8 to get the exact place where u-boot got stuck.


For custom board bringing up we suggest customers use DDRv tool to do DDR controller configuration optimization and validation.

For how to use QCVS and DDRv tool, please refer to the user manual from http://www.nxp.com/docs/en/user-guide/QCVS_DDR_User_Guide.pdf.

 If there is DDR SPD on your target board, please use read from SPD option when create a QorIQ Configuration Project.

 If no SPD, after creating the QCVS project, please configure DDR Properties in the project according to DDR datasheet, generate DDR configuration parameters from Project->Generate Processor Expert Code, then use DDRv tool to optimize and validate the generated DDR controller configuration parameters.


If there is SPD on your target board, please modify udimm0 in board/freescale/ls1046ardb/ddr.h with the optimized parameters calculate by DDRv tool.


If there is no SPD on the custom board, you also need to calculate DDR raw timing according to the optimized DDR controller configuration parameters, please refer to ddr_raw_timing definition in board/freescale/ls1043ardb/ddr.c.


Have a great day,
TIC

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j_wallace
Contributor II

Hello Gabor Kocsis,

Could you please give feedback about your issue?

Best Regards.

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