Mismatching between ADS MODEL of MRFE6VP61K25HSR6 ADS Product Model Design Kit With MRFE6VP61K25HSR6 LDMOS

[ajaysingh]

I was using your MRFE6VP61K25HSR6 ADS Product Model Design Kit, whatever Current and voltage characteristics i am getting from this model, is not matching with your MRFE6VP61K25HSR6 LDMOS chracterized results.  On current and Threshold voltage are not matching with measured result of your MRFE6VP61K25HSR6 LDMOS device. Can you help me out what can be the reason of mismatching.

[LPP]

> On current and Threshold voltage are not matching

What is the problem? I do not see critical contradictions of simulated results with datasheet values.

I see that simulated threshold is slightly less than datasheet minimum voltage 1.7V. But it is not important.

Please note that production variance of the threshold voltage is large. Anyway, each LDMOS transistor will require a
unique gate voltage setting for the optimum drain current in a particular power amplifier design.

Gate bias should be tuned to achieve the target quiescent current. By doing that you will eliminate the influence of the gate threshold production variance on the RF performance. So, it doesn't matter what is the actual value of the threshold.

Also, note that the model doesn't account for production variance of any parameter. The model represents only one typical sample.

Have a great day,
Pavel

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