The first published Electrical Characteristics document for the P1011, P1011EC Rev 0 08/2011, did not reference READY_P1. Instead, that pin was listed as NC109, and seemingly had no role in POR configuration.
Among the changes that P1011EC Rev. 1, 03/2012 introduced, it states
In Table 1, replaced the signals NC107, NC108, and NC109 (along with their details, such as Package Pin Number, Pin Type, and Power Supply) with the signals CKSTP_IN1_B, CKSTP_OUT1_B, and READY_P1 respectively.
where it is listed as a Debug Output, but a table footnote states
Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. This pin is described as an I/O for boundary scan.
In the P1020RM, READY_P1 also serves as a POR configuration pin cfg_core1_pll2, for Core1 PLL, (unused and unpowered on the P1011), and the Core 1 PLL setting should not have any bearing on Core 0, but appears to affect behaviour of Core 0 access to L2 RAM for certain Core 0 and 1 PLL combinations. The effect is observed as greater timing jitter on timed code function execution. The observation leads to speculation that the Core 1 PLL is factored into the Coherency module configuration in some way that isn't obvious from the datasheet. Has anyone else observed and better characterised this?