Hi,
Thank you for your reply. I try your method, but it dosen`t work.
The flash.ld file of the application is as below:
MEMORY
{
flash_rchw : org = 0x01180000, len = 0x4
cpu0_reset_vec : org = 0x01180004, len = 0x4
m_text : org = 0x01180010, len = 510K
m_data : org = 0x40000000, len = 384K
local_dmem : org = 0x50800000, len = 64K
}
And please look my AppJump.S, is there any fault?
/*
* AppJump.S**********************************************
*
*/
.section .text, "ax"
.globl _AppExecute
_AppExecute:
;#but first check, if there's valid boot header at address 0x01000000
;#load address of boot header to r12
e_lis r12, 0x0118
e_or2i r12, 0x0000
;#load upper half of boot header word to r0
;#(lower half is application dependent)
e_lhz r0, 0(r12)
;#boot header should be 0x015A
e_cmpl16i r0, 0x015A
;#if the boot header is not valid, execute bootloader
// e_bne _BootLd ;#Bootloader_Main
;#if the boot header is valid, execute application
;#********************************* Enable BTB ********************************
;# Flush & Enable BTB - Set BBFI bit in BUCSR
e_li r3, 0x201
mtspr 1013, r3
se_isync
;#**************************** Init Core Registers ****************************
;# The E200Z4 core needs its registers initialising before they are used
;# otherwise in Lock Step mode the two cores will contain different random data.
;# If this is stored to memory (e.g. stacked) it will cause a Lock Step error.
;# GPR's 0-31
e_li r0, 0
e_li r1, 0
e_li r2, 0
e_li r3, 0
e_li r4, 0
e_li r5, 0
e_li r6, 0
e_li r7, 0
e_li r8, 0
e_li r9, 0
e_li r10, 0
e_li r11, 0
e_li r12, 0
e_li r13, 0
e_li r14, 0
e_li r15, 0
e_li r16, 0
e_li r17, 0
e_li r18, 0
e_li r19, 0
e_li r20, 0
e_li r21, 0
e_li r22, 0
e_li r23, 0
e_li r24, 0
e_li r25, 0
e_li r26, 0
e_li r27, 0
e_li r28, 0
e_li r29, 0
e_li r30, 0
e_li r31, 0
;# Init any other CPU register which might be stacked (before being used).
mtspr 1, r1 ;#XER
mtcrf 0xFF, r1
mtspr CTR, r1
mtspr 272, r1 ;#SPRG0
mtspr 273, r1 ;#SPRG1
mtspr 274, r1 ;#SPRG2
mtspr 275, r1 ;#SPRG3
mtspr 58, r1 ;#CSRR0
mtspr 59, r1 ;#CSRR1
mtspr 570, r1 ;#MCSRR0
mtspr 571, r1 ;#MCSRR1
mtspr 61, r1 ;#DEAR
mtspr 63, r1 ;#IVPR
mtspr 256, r1 ;#USPRG0
mtspr 62, r1 ;#ESR
mtspr 8, r31 ;#LR
;#load address of reset vector to r12
e_lis r12, 0x0118
e_or2i r12, 0x0004
;#load reset vector to r0
e_lwz r0, 0(r12)
;#move reset vector to link register
mtlr r0
;#branch to address in link register
se_blrl
_BootLd:
e_lis r12, Bootloader_Main@h
e_or2i r12, Bootloader_Main@l
;#move Bootloader_Main Address to link register
mtlr r12
;#branch to address in link register
se_blrl
/*****************************************************************************/
