AnsweredAssumed Answered

MPC5746C DSPI (slave SPI mode) lost one byte between frames if underflow occurred

Question asked by wesley xie on May 22, 2018
Latest reply on May 31, 2018 by wesley xie

Hi, NXP guys

Kirk HumphriesMandar JoshiwesDhaval ShahRHinnenJames TrudeauMartin Wennerstromvcentea1

 

In our project, we configure MPC5746C DSPI to work in slave SPI mode,

the Master side clock is 5MHz, read 32byte with continuous chip select asserted.

I found that , it always lost the certain byte between 32-bytes frames if underflow occurred before MPC5746C switch to next DMA transfer (DMA interrupt take time to response and handle).

 

PS:

1. if I down the Master CLK to 1MHz (no underflow between DMA transfer), this issue disappeared.

2. if the Master side switched the CS to non-continuous mode (deassert CS each byte), still underflow between DMA transfer, but this issue disappeared. 

 

Attachments

Outcomes