Hi, NXP guys
In our project, we configure MPC5746C DSPI to work in slave SPI mode,
the Master side clock is 5MHz, read 32byte with continuous chip select asserted.
I found that , it always lost the certain byte between 32-bytes frames if underflow occurred before MPC5746C switch to next DMA transfer (DMA interrupt take time to response and handle).
1. if I down the Master CLK to 1MHz (no underflow between DMA transfer), this issue disappeared.
2. if the Master side switched the CS to non-continuous mode (deassert CS each byte), still underflow between DMA transfer, but this issue disappeared.