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S32K144EVB: SPI Clock Not Accurate

Question asked by Mahmoud Sherrah on May 19, 2018
Latest reply on Jun 5, 2018 by Daniel Martynek

My SPI driver on S32K144EVB-Q100 is working. However, as SPI master, the output master clock is not very accurate.


- The SysClock is 80MHz (normal run mode)

- I set LPSPI0 input clock to SPLLDIV2  which sets LPSPI0 functional clock it to 40MHz

- I set PRESCALE in LPSPI0->TCR to 0 (divided by 1), so SPI clock is still 40MHz

- I set SCKDIV in LPSPI0->CCR to 1 (1 + 2(mandatory) = 3), so SPI clock is 40MHz/3 = 13.3MHz


I observe the output clock using a 250Ms/S PC-based oscilloscope (Saleae) and the clock is not exactly 13.3MHz.

In one transmission it is ~12.5MHz, in the next transmission it is ~13.1MHz. It is never constant and it is never exactly 13.3MHz.


My question is: is this a common attribute of SPI clocks in general? is there always a margin of error that is unavoidable? Or is it a problem of 13.3MHz not being a whole number (like 8MHz or 4MHz.. etc)?