AnsweredAssumed Answered

i.MX6DQ IPU Support For MIPI DSI Command Mode

Question asked by David Ziemba on May 19, 2018
Latest reply on May 24, 2018 by igorpadykov

On our custom i.MX6Q-based board, we have a MIPI DSI display (H245QBN02.0, 1 data lane) that operates in command mode only. We are able to control this display in MIPI DSI command mode from the i.MX6Q ARM platform, but that’s a bit slow and consumes ARM platform CPU cycles. We therefore want to take advantage of the i.MX6Q’s IPU’s ability to send display data more autonomously via the MIPI DSI interface, with little or no intervention by the ARM platform.


According to the i.MX6DQ reference manual, Rev. 2, 6/2014, MIPI command mode is supported by the IPU, via the IPU’s Asynchronous Access Mode. However, it’s not clear how this is done: It’s not obvious which IPU registers to configure to support command/asynchronous mode via the IPU and MIPI DSI interface, such that the display can be operated in a fashion similar to video mode, where little or no ARM platform intervention is required.


I'll continue looking into this, but I’m hoping that someone here can point me to an app note and/or sample code that provides detailed guidance regarding how to set up the IPU and MIPI DSI interface to support this Asynchronous Access Mode, for support of MIPI DSI command mode on our display.


(This question may be a duplicate; I posted an earlier version of the question, but noticed that I posted it only in the "Using Our Community" section. This is my attempt at posting it to the NXP/i.MX technical forum.)