I have 16-bit SRAM connected to K22 via Flexbus. Port size of Flexbus is set to 16-bit. No delays are introduced in write/read cycles (I mean WS/ASET/RDAH/WRAH re all set to 0). This is my configuration:
FB->CS.CSCR = FB_CSCR_PS(2)
I write 32 bit integer into my memory:
volatile int *sram;
sram = SRAM_START_ADDRESS;
sram = 0;
I can see that writing first part of my 32 bit integer takes only 3 flexbus clock cycles. (in the picture you can see three 32 bit integer writes to the 16 bit memory)
In all documents I read flexbus read/write cycles take 4 clock cycles min. Can you please help me in understanding this 3 clock cycle write?