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Flexbus write cycle

Question asked by Dusek on May 17, 2018
Latest reply on May 24, 2018 by Dusek

Hi,

I have 16-bit SRAM connected to K22 via Flexbus. Port size of Flexbus is set to 16-bit. No delays are introduced in write/read cycles (I mean WS/ASET/RDAH/WRAH re all set to 0). This is my configuration:

 

FB->CS[0].CSCR = FB_CSCR_PS(2)
| FB_CSCR_BLS_MASK
| FB_CSCR_ASET(0x0)
| FB_CSCR_RDAH(0x0)
| FB_CSCR_WRAH(0x0)
| FB_CSCR_AA_MASK
| FB_CSCR_WS(0x0)
;

 

I write 32 bit integer into my memory:

 

volatile int *sram;
sram = SRAM_START_ADDRESS;

sram[0] = 0;

 

I can see that writing first part of my 32 bit integer takes only 3 flexbus clock cycles. (in the picture you can see three 32 bit integer writes to the 16 bit memory)

 

 

In all documents I read flexbus read/write cycles take 4 clock cycles min. Can you please help me in understanding this 3 clock cycle write?

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