I use 74LVC574A to latch address on Flexbus on rising edge of ALE signal. However latching (and thus my interface to SRAM) works only if I delay a little the ALE signal (the delay is achived by connecting 330 pF capacitor between ALE and GND). The problem is that the latch sometimes and on some address lines latch old value of address lines, because the change of the address happens with rising edge of ALE signal and the new address value is missed by a short moment.
So, is latching supposed to be working with ALE directly connected to CP pin of D flip-flop? If so, then there is something wrong with my PCB. My Address/data lines are directly connected to 4 components - MCU, latch, SRAM and CPLD (Altera MAX V). The length of the lines is 3 inch max. Maybe too much capacitance on these lines, which delays signal on address lines causing latch of old values?