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i.MX6UL+LPDDR2 DDR Stress test failed, asking for help!

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i.MX6UL+LPDDR2 DDR Stress test failed, asking for help!

‎05-09-2018 12:28 AM
757 Views
tiantianhuang
Contributor I

i.MX6UL+LPDDR2 DDR Stress test failed, asking for help!

The Environment is:

   platform: imx6UL (9x9)

   DDR_Stress_Tester version : V2.80

   PC: win10 64bit

   LPDDR2:   ISSI IS43LD16640C-25BLI

The inc file is from MX6UL_LPDDR2_Script_Aid V0.02.xlsx, the setting is

Device Information
Manufacturer:ISSI
Memory part number:IS43LD16640C-25BLI
Memory type:LPDDR2-800
DRAM single die density (Gb)1
DRAM density(Gb)1
Number of Chip Selects used1
DRAM density per CS (Gb)1
DRAM Bus Width Per CS16
Number of Banks8
Number of ROW Addresses13
Number of COLUMN Addresses10
System Information
i.Mx Parti.MX6UL
DRAM Clock Freq (MHz)400
DRAM Clock Cycle Time (ns)2.5
PCB Parameters
DRAM DSE Setting - DQ/DQM (ohm)48
DRAM DSE Setting - CA/CTL (ohm)48
DRAM DSE Setting - CK (ohm)48
DRAM DSE Setting - DQS (ohm)48

(  the impedance of my board is designed with 50 ohm)

The calibration result at 400MHz is :


============================================
DDR Stress Test (2.6.0)
Build: Jan 24 2018, 14:19:36
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 UltraLite(0x64)
Internal Revision = TO1.2
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000050
SRC_SBMR2(0x020d801c) = 0x02000041
============================================

ARM Clock set to 528MHz

============================================
DDR configuration
DDR type is LPDDR2 in 1-channel mode.
Data width: 16, bank num: 8
Row size: 13, col size: 10
Chip select CSD0 is used
Density per chip select: 128MB
Density per channel: 128MB
============================================

Current Temperature: 43
============================================

DDR Freq: 396 MHz

Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 01:byte 0 fail.
result 11:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x11
ABS_OFFSET=0x04040404 result[01]=0x11
ABS_OFFSET=0x08080808 result[02]=0x11
ABS_OFFSET=0x0C0C0C0C result[03]=0x11
ABS_OFFSET=0x10101010 result[04]=0x11
ABS_OFFSET=0x14141414 result[05]=0x11
ABS_OFFSET=0x18181818 result[06]=0x11
ABS_OFFSET=0x1C1C1C1C result[07]=0x11
ABS_OFFSET=0x20202020 result[08]=0x11
ABS_OFFSET=0x24242424 result[09]=0x11
ABS_OFFSET=0x28282828 result[0A]=0x10
ABS_OFFSET=0x2C2C2C2C result[0B]=0x10
ABS_OFFSET=0x30303030 result[0C]=0x10
ABS_OFFSET=0x34343434 result[0D]=0x10
ABS_OFFSET=0x38383838 result[0E]=0x10
ABS_OFFSET=0x3C3C3C3C result[0F]=0x10
ABS_OFFSET=0x40404040 result[10]=0x10
ABS_OFFSET=0x44444444 result[11]=0x10
ABS_OFFSET=0x48484848 result[12]=0x10
ABS_OFFSET=0x4C4C4C4C result[13]=0x10
ABS_OFFSET=0x50505050 result[14]=0x11
ABS_OFFSET=0x54545454 result[15]=0x10
ABS_OFFSET=0x58585858 result[16]=0x10
ABS_OFFSET=0x5C5C5C5C result[17]=0x10
ABS_OFFSET=0x60606060 result[18]=0x10
ABS_OFFSET=0x64646464 result[19]=0x10
ABS_OFFSET=0x68686868 result[1A]=0x10
ABS_OFFSET=0x6C6C6C6C result[1B]=0x10
ABS_OFFSET=0x70707070 result[1C]=0x11
ABS_OFFSET=0x74747474 result[1D]=0x11
ABS_OFFSET=0x78787878 result[1E]=0x11
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11

Byte 0: (0x28 - 0x4c), middle value:0x3a
ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

The calibration result at 300MHz is :

============================================
DDR Stress Test (2.6.0)
Build: Jan 24 2018, 14:19:36
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 UltraLite(0x64)
Internal Revision = TO1.2
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000050
SRC_SBMR2(0x020d801c) = 0x02000041
============================================

ARM Clock set to 528MHz

============================================
DDR configuration
DDR type is LPDDR2 in 1-channel mode.
Data width: 16, bank num: 8
Row size: 13, col size: 10
Chip select CSD0 is used
Density per chip select: 128MB
Density per channel: 128MB
============================================

Current Temperature: 56
============================================

DDR Freq: 297 MHz

Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 01:byte 0 fail.
result 11:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x11
ABS_OFFSET=0x04040404 result[01]=0x11
ABS_OFFSET=0x08080808 result[02]=0x11
ABS_OFFSET=0x0C0C0C0C result[03]=0x11
ABS_OFFSET=0x10101010 result[04]=0x11
ABS_OFFSET=0x14141414 result[05]=0x00
ABS_OFFSET=0x18181818 result[06]=0x00
ABS_OFFSET=0x1C1C1C1C result[07]=0x00
ABS_OFFSET=0x20202020 result[08]=0x00
ABS_OFFSET=0x24242424 result[09]=0x00
ABS_OFFSET=0x28282828 result[0A]=0x00
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00
ABS_OFFSET=0x30303030 result[0C]=0x00
ABS_OFFSET=0x34343434 result[0D]=0x00
ABS_OFFSET=0x38383838 result[0E]=0x00
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00
ABS_OFFSET=0x40404040 result[10]=0x00
ABS_OFFSET=0x44444444 result[11]=0x00
ABS_OFFSET=0x48484848 result[12]=0x00
ABS_OFFSET=0x4C4C4C4C result[13]=0x00
ABS_OFFSET=0x50505050 result[14]=0x00
ABS_OFFSET=0x54545454 result[15]=0x00
ABS_OFFSET=0x58585858 result[16]=0x00
ABS_OFFSET=0x5C5C5C5C result[17]=0x00
ABS_OFFSET=0x60606060 result[18]=0x00
ABS_OFFSET=0x64646464 result[19]=0x00
ABS_OFFSET=0x68686868 result[1A]=0x00
ABS_OFFSET=0x6C6C6C6C result[1B]=0x00
ABS_OFFSET=0x70707070 result[1C]=0x00
ABS_OFFSET=0x74747474 result[1D]=0x11
ABS_OFFSET=0x78787878 result[1E]=0x11
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11

Byte 0: (0x14 - 0x70), middle value:0x42
Byte 1: (0x14 - 0x70), middle value:0x42

MMDC0 MPRDDLCTL = 0x40404242

Starting Write calibration...

ABS_OFFSET=0x00000000 result[00]=0x11
ABS_OFFSET=0x04040404 result[01]=0x11
ABS_OFFSET=0x08080808 result[02]=0x11
ABS_OFFSET=0x0C0C0C0C result[03]=0x11
ABS_OFFSET=0x10101010 result[04]=0x11
ABS_OFFSET=0x14141414 result[05]=0x11
ABS_OFFSET=0x18181818 result[06]=0x11
ABS_OFFSET=0x1C1C1C1C result[07]=0x11
ABS_OFFSET=0x20202020 result[08]=0x11
ABS_OFFSET=0x24242424 result[09]=0x11
ABS_OFFSET=0x28282828 result[0A]=0x11
ABS_OFFSET=0x2C2C2C2C result[0B]=0x11
ABS_OFFSET=0x30303030 result[0C]=0x11
ABS_OFFSET=0x34343434 result[0D]=0x10
ABS_OFFSET=0x38383838 result[0E]=0x00
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00
ABS_OFFSET=0x40404040 result[10]=0x00
ABS_OFFSET=0x44444444 result[11]=0x00
ABS_OFFSET=0x48484848 result[12]=0x00
ABS_OFFSET=0x4C4C4C4C result[13]=0x00
ABS_OFFSET=0x50505050 result[14]=0x00
ABS_OFFSET=0x54545454 result[15]=0x00
ABS_OFFSET=0x58585858 result[16]=0x00
ABS_OFFSET=0x5C5C5C5C result[17]=0x00
ABS_OFFSET=0x60606060 result[18]=0x00
ABS_OFFSET=0x64646464 result[19]=0x00
ABS_OFFSET=0x68686868 result[1A]=0x00
ABS_OFFSET=0x6C6C6C6C result[1B]=0x00
ABS_OFFSET=0x70707070 result[1C]=0x00
ABS_OFFSET=0x74747474 result[1D]=0x00
ABS_OFFSET=0x78787878 result[1E]=0x00
ABS_OFFSET=0x7C7C7C7C result[1F]=0x00

Byte 0: (0x34 - 0x7c), middle value:0x58
Byte 1: (0x38 - 0x7c), middle value:0x5a

MMDC0 MPWRDLCTL = 0x40405A58


MMDC registers updated from calibration

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x40404242

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x40405A58


Success: DDR calibration completed!!!

The stress test result at 150MHz is :
============================================
DDR Stress Test (2.6.0)
Build: Jan 24 2018, 14:19:36
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 UltraLite(0x64)
Internal Revision = TO1.2
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000050
SRC_SBMR2(0x020d801c) = 0x02000041
============================================

ARM Clock set to 528MHz

============================================
DDR configuration
DDR type is LPDDR2 in 1-channel mode.
Data width: 16, bank num: 8
Row size: 13, col size: 10
Chip select CSD0 is used
Density per chip select: 128MB
Density per channel: 128MB
============================================


DDR Stress Test Iteration 1
Current Temperature: 58
============================================

DDR Freq: 148 MHz
t0.1: data is addr test
Address of failure(step2): 0x800000f4
Data was: 0x800001f4
But pattern should match address
Error: failed to run stress test!!!

So the stress test will fail just only at 150MHz, but the calibration will pass at 300MHz. Please help me and tell me the possible resolving way, Thanks! 

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‎05-09-2018 03:42 AM
573 Views
igorpadykov
NXP Employee
NXP Employee

Hi tiantian

for 400MHz calibration failure reason may be board noise, also one can

check lpddr2 routing rules usingTable 19. DDR trace routing guidelinesi.MX7D User Guide

https://www.nxp.com/docs/en/user-guide/IMX7DSHDG.pdf 

For error :

Address of failure(step2): Address of failure(step2): 0x800000f4
Data was: 0x800001f4

one can write/read with jtag 0x800000f4 data on that address
and check with oscilloscope erroneous bit 0x80000 "1" f4 .

Best regards
igor
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