Joan Fontanet

LPC4078 ADC: Hardware-Triggered conversion and A/D Clock

Discussion created by Joan Fontanet on Apr 27, 2018
Latest reply on Apr 30, 2018 by Joan Fontanet

I'm developping code for managing the ADC of the LPC4078. As introduction, I need to read 7 channels in non-continuous adquisition and 1 channel in continuous acquisition at 100Ksps.


First , I want to bring out that the LPC Open library is setting the A/D Clock at 15Mhz when setting the adcRate at 400Ksps while using the APB clock (PCLK) at 60MHz. The LPCOPEN library is setting the CLKDIV of 4. The A/D Clock at 15Mhz is causing unexpected adcRate. I've set the CLKDIV at 5 to achieve a 12 Mhz clock which is within the 12.4MHz which points out the user manual. Using the 12MHz clock, I'm achiving the expected adcRate.


For my purpose I'm triggering the ADC conversion through the Match 1 of the Timer 0 at a sample rate of 100Ksps and  setting the A/D Clock at 12MHz. Also, I enable the interrupt of ADC to read the continuous acquisition channel. For the remaining Non-continuous acquisition channels I'm thinking to enable and disable those channels when required.


Muy set up works fine when I have enable only the continuous acquisition channel. The problems comes out when I enable a second channel. When I'm enabling a second channel I'm acquiring a different sample rate for the continous adquisition channel, and I don't understand why. I'm going deep reading the user manual, and the only point I think can cause a problem is the following:


"Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01."


Do you think that may be while using the triggering of the ADC conversion through the Match of the Timer can only be 1 ADC channel  enabled ? altough it is hardware and not software controlled.


The sampling rate of the continuous adquisition channel should not be modified for only two channels enabled with a 31 clock ADC conversion and 12MHz ADC clock, which at least should support 3 enabled channels.


Thanks in advance