Sten Siren

IIC clock frequency on 9S12XDT256 (0L15Y)

Discussion created by Sten Siren on Oct 29, 2008
During testing of my system, I happened to measure the frequency of the IIC-clock generated by the uC (SCL0 = pin 98 on a 112-pin package), and it was not correct!
I use a 4MHz oscillator and I am using the PLL to generate a 20MHz bus frequency (SYNR = 4, REFDV = 0) and I have checked the frequency on the ECLK-pin to be 20.00MHz.
During initialisation of the IIC-interface I set IIC0_IBFD = 0x43, which should, according to the data sheet (rev. 2.17), give that the SCL Divider = 52, which in turn should give a IIC-clock of 384.6Kz. But I do measure a frequency of 400.1kHz! I did also check on another board with a 9S12DT128 (1L59W) with the same settings, and on that the frequency is 384.7kHz.
As an attempt to figure out what is wrong with the XDT-version, I did a set of tests with settings that all should give a frequency of 250KHz (divider 80), and the results are as follows:
IIC0_IBFD = 0x14 -> 250.1kHz
IIC0_IBFD = 0x18 -> 250.1kHz
IIC0_IBFD = 0x47 -> 255.5kHz
IIC0_IBFD = 0x4b -> 250.1kHz
IIC0_IBFD = 0x80 -> 277.8kHz
Have I misunderstood the Table 9-5 on pages 401..405 of the data sheet or should the IIC-clock be 250kHz in all above cases?
I didn't find any errata for this chip regarding IIC clocks.
PS. I am measuring the frequency with a 200MHz Fluke Scopemeter 199C.