AnsweredAssumed Answered

How to make the SIUL Extern Interrupt work in MPC5744P

Question asked by five number on Apr 26, 2018
Latest reply on May 1, 2018 by yash vardhan

      I configured SIUL Extern Interrupt funtion as like Datasheet descript(chater 16.3.4.1), but the funtion not work. The SIUL Extern Interrupt funtion configuration as follows:

Step 1: Mask interrupts by clearing the EIREn bits in DIRER0, configured as SIUL2.DIRER0.R = 0x00000000;

 

Step 2: Select the pin polarity by setting the appropriate IREEn bits in IREER0 and the appropriate IFEEn bits in IFEER0 as desired. Configured as SIUL2.IFEER0.R = 0x80000000 and SIUL2.IREER0.R = 0x80000000;

 

Step 3: Configure the appropriate bits in the MSCR[0:511] register. Configured as SIUL2.MSCR[93].R = 0x00090000 and

            SIUL2.IMCR[204].R = 0x00000001;

 

Step 4:  Select the request desired between DMA or Interrupt by writing the appropriate DIRSn bits in                                         DIRSR0. Configured as SIUL2.DIRSR0.R = 0x80000000;

 

 Step 5: Select the desired glitch filter setup for the pins. Configured as SIUL2.IFMCR[31].B.MAXCNT = 5 ,               SIUL2.IFCPR.B.IFCP = 8 and SIUL2.IFER0.R = 0x80000000; 

 

Step 6: Write to EIFn bits in DISR0 to as desired to clear any flags. Configured as SIUL2.DISR0.R = 0x80000000;

 

Step 7:  Enable the interrupt pins by setting the appropriate EIREn bits in DIRER0. Configured as 

              SIUL2.DIRER0.R = 0x80000000;

 

Is there anything else that needs to be configured or my configuration have something wrong?

 

 

in the end,paste my initialize source code as follows and give my best wishes to everyone!

void External_Interrupt_3_Init(void)
{
   SIUL2.DIRER0.R = 0x00000000;

   SIUL2.IFEER0.R = 0x80000000;          //enable REQ31 rising-edge triggered event

   SIUL2.IREER0.R = 0x80000000;          //enable REQ31 Falling-Edge triggered Event
   SIUL2.MSCR[93].R = 0x00090000;
   SIUL2.IMCR[204].R = 0x00000001;

   SIUL2.DIRSR0.R = 0x80000000;

   SIUL2.IFMCR[31].B.MAXCNT = 5;

   SIUL2.IFCPR.B.IFCP = 8;
   SIUL2.IFER0.R = 0x80000000;       // enabled Filter

   SIUL2.DISR0.R = 0x80000000;       //clear REQ31 interrupt

   SIUL2.DIRER0.R = 0x80000000;
}

Outcomes