T4160 DDR3 clock

[logifrancis]

Hi, 

I am doing a T4160 based design. I am using DDR3 chip down configuration (not DIMM).  I am using X16 DDR3 chips. So for 64 bit +ECCC (72 bit), we have 5 DDR3 chips. DDR clock signal from T4160 DDR controller is connected to 5 chips.I saw that in Reference manual, 11.5.4.1 Clock distribution, it is mentioned that " If running with many devices, zero-delay PLL clock buffers, JEDEC-JESD82 standard, should be used. These buffers were designed for DDR applications." As per this do i have to use zero delay PLL clock buffer in our design (5 chips)?

[r8070z]

Have a great day,

I suppose that fly-by topology is used for address/command/control and clock groups. The routing in fly-by topology should go from chip 1 to chip 5 and can be in the order that is most convenient for the board design. The fly-by topology routing of address/command/ control and clock groups must end at the termination resistors that are after chip 5. I.e. you need only for one DDR clock output in your design. Please see more details in nxp application note “Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces” (AN3940). It is available on the nxp site.

By the way the DDR controller already has clock buffer with 3 outputs (MCK/MCK_B[0:2]). The 11.5.4.1 section in the next (second) item says:”A 72 bit x 64  Mbytes DDR bank has 9-byte-wide DDR chips, resulting in 18 DDR chips in a two-bank system. In this case, each MCK/MCK_B signal pair should drive exactly nine devices”

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