I am doing a T4160 based design. I am using DDR3 chip down configuration (not DIMM). I am using X16 DDR3 chips. So for 64 bit +ECCC (72 bit), we have 5 DDR3 chips. DDR clock signal from T4160 DDR controller is connected to 5 chips.I saw that in Reference manual, 184.108.40.206 Clock distribution, it is mentioned that " If running with many devices, zero-delay PLL clock buffers, JEDEC-JESD82 standard, should be used. These buffers were designed for DDR applications." As per this do i have to use zero delay PLL clock buffer in our design (5 chips)?