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MPC5748G Bootloader Configuration (DEVKIT-MPC5748G)

Question asked by Navinar Savad on Apr 20, 2018
Latest reply on Apr 23, 2018 by Navinar Savad

Hi,

   I am working on creating a bootloader application for the MPC5748G devkit board, and I am using the S32 IDE. The requirements are as below:

  1. The bootloader, on bootup will check a flash location for a word indicating whether a new firmware is available or not (This word is written by the main firmware on receiving a new firmware and saving it to flash).
  2. If available, it will copy the new firmware and replace it with the old firmware(user application). 
  3. If unavailable, bootloader will boot the current firmware.
  4. The firmware update process takes place via ETHERNET from the user application, not serial interface.

 

I have downloaded the Bootloader_MPC5748G bootloader code from the Example codes, but need some help as I am working on bootloader for the first time, and the schedule is tight. I have modified the linker scripts of the user application and the bootloader. 

 

The main question I have is how to jump to the user application from the bootloader after checking the word.

It would be very helpful if you could provide some insight into this. I want to do the jump from the main function itself, and I was unable to find any info in the bootloader application regarding this.  I have attached the bootloader code here. 

 

The bootloader's linker script is:

Bootloader

SRAM_SIZE = 128K;
SRAM_BASE_ADDR = 0x40000000;
MEMORY
{
flash_rchw : org = 0x00F8C000, len = 16K
m_text : org = 0x1000000, len = 256K
m_data : org = 0x40000000, len = 128K
}

 

The user application's linker scripts are as follows: 

 

Core 0
SRAM_SIZE = 256K;
SRAM_BASE_ADDR = 0x40020000;
MEMORY
{

flash_rchw : org = 0x00FA0000, len = 0x4
cpu0_reset_vec : org = 0x00FA0000+0x10, len = 0x4
cpu1_reset_vec : org = 0x00FA0000+0x14, len = 0x4
cpu2_reset_vec : org = 0x00FA0000+0x04, len = 0x4

m_text : org = 0x1040000, len = 1856K
m_data : org = 0x40020000, len = 256K
}

 

Core 1
SRAM_SIZE = 256K;
SRAM_BASE_ADDR = 0x40060000;
MEMORY
{

flash_rchw : org = 0x00FA0000, len = 0x4
cpu0_reset_vec : org = 0x00FA0000+0x10, len = 0x4
cpu1_reset_vec : org = 0x00FA0000+0x14, len = 0x4
cpu2_reset_vec : org = 0x00FA0000+0x04, len = 0x4

m_text : org = 0x1210000, len = 1856K
m_data : org = 0x40060000, len = 256K
}

 

core 2
SRAM_SIZE = 128K;
/* Define SRAM Base Address */
SRAM_BASE_ADDR = 0x400A0000;

MEMORY
{

flash_rchw : org = 0x00FA0000, len = 0x4
cpu0_reset_vec : org = 0x00FA0000+0x10, len = 0x4
cpu1_reset_vec : org = 0x00FA0000+0x14, len = 0x4
cpu2_reset_vec : org = 0x00FA0000+0x04, len = 0x4

m_text : org = 0x13E0000, len = 1600K
m_data : org = 0x400A0000, len = 128K
}

 

 

Any help would be greatly appreciated.

 

 Stanislav Sliva  Udit Salunke  Lukas Zadrapa Martin Kovar Jiri Kral 

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